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FEATURES Complete Analog I/O Port for Voiceband DSP Applications Linear-Coded 16-Bit Sigma-Delta ADC Linear-Coded 16-Bit Sigma-Delta DAC On-Chip Anti-Aliasing and Anti-lmaging Filters On-Chip Voltage Reference 8 kHz Sampling Frequency Twos Complement Coding 65 dB SNR + THD Programmable Gain on DAC and ADC Serial Interface To DSP Processors 24-Pin DlP/28-Lead SOIC Single 5 V Power Supply
VOICEBAND ANALOG INPUT A MUX VOICEBAND ANALOG INPUT B
Voiceband Signal Port AD28MSP02
FUNCTIONAL BLOCK DIAGRAM
16-BIT SIGMADELTA ADC DIGITAL DATA AND CONTROL VOLTAGE REFERENCE SERIAL PORT
+20dB AMP
DIFFERENTIAL ANALOG OUTPUT
PGA
16-BIT SIGMADELTA DAC
GENERAL DESCRIPTION
Analog Input Amplifiers
The AD28MSP02 Voiceband Signal Port is a complete analog front end for high performance voiceband DSP applications. Compared to traditional -law and A-law codecs, the AD28MSP02's linear-coded ADC and DAC maintain wide dynamic range while maintaining superior SNR and THD. A sampling rate of 8.0 kHz coupled with 65 dB SNR + THD performance make the AD28MSP02 attractive in many telecom and speech processing applications, for example digital cellular radio and high quality telephones. The AD28MSP02 simplifies overall system design by requiring only a single +5 V power supply. The inclusion of on-chip anti-aliasing and anti-imaging filters, 16-bit sigma-delta ADC and DAC, and programmable gain amplifiers ensures a highly integrated and compact solution to voiceband analog processing requirements. Sigma-delta conversion technology eliminates the need for complex off-chip antialiasing filters and sample-and-hold circuitry. The AD28MSP02's serial I/O port provides an easy interface to host DSP microprocessors such as the ADSP-2101, ADSP-2105 and ADSP-2111. The AD28MSP02 is available in a 24-pin, 0.3" plastic DIP and a 28-lead SOIC package.
FUNCTIONAL DESCRIPTION
The two analog input amplifiers (NORM, AUX) are internally biased by an on-chip voltage reference in order to allow operation of the AD28MSP02 with a single +5 V power supply. An analog multiplexer selects either the NORM or AUX amplifier as the input to the ADC's sigma-delta modulator. The optional 20 dB preamplifier may be used to increase the signal level; the preamplifier can be inserted before the modulator or can be bypassed. Input signal level to the sigma-delta modulator should not exceed VINMAX, which is specified under "Analog Interface Electrical Characteristics." Refer to "Analog Input" in the "Design Considerations" section of this data sheet for more information. The input multiplexer and 20 dB preamplifier are configured by Bits 0 and 1 (IPS, IMS) of the AD28MSP02's control register. If the multiplexer setting is changed while an input signal is being processed, the ADC's output must be allowed time to settle to ensure that the output data is valid.
ADC
Figure 1 shows a block diagram of the AD28MSP02.
A/D CONVERSION
The ADC consists of a 2nd-order analog sigma-delta modulator, an anti-aliasing decimation filter, and a digital high-pass filter. The sigma-delta modulator noise-shapes the signal and produces 1-bit samples at a 1.0 MHz rate. This bit stream, which represents the analog input signal, is fed to the anti-aliasing decimation filter.
Decimation Filter
The A/D conversion circuitry of the AD28MSP02 consists of two analog input amplifiers, an optional 20 dB preamplifier, and a sigma-delta analog-to-digital converter (ADC). The analog input signal to the AD28MSP02 must be ac-coupled.
The anti-aliasing decimation filter contains two stages. The first stage is a sinc4 digital filter that increases resolution to 16 bits and reduces the sample rate to 40 kHz. The second stage is an IIR low-pass filter.
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AD28MSP02
VFB NORM VINNORM NORM INPUT AMP VFB AUX VIN AUX AUX INPUT AMP VOLTAGE REFERENCE CONTROL REGISTER SERIAL PORT SCLK 16-BIT SIGMA-DELTA DAC VOUT P PGA VOUTN OUTPUT DIFFERENTIAL AMP ANALOG SMOOTHING FILTER 1 1.0 MHz DIGITAL SIGMA-DELTA MODULATOR 16 1.0 MHz ANTI-IMAGING INTERPOLATION FILTER 16 8.0 kHz DIGITAL HIGH-PASS FILTER 16 SDI 8.0 kHz SDIFS MUX +20dB AMP 16-BIT SIGMA-DELTA ADC ANALOG SIGMA-DELTA MODULATOR 1 ANTI-ALIASING DECIMATION FILTER 16 DIGITAL HIGH-PASS FILTER 16 SDO 8.0 kHz DATA/ CNTRL SDOFS
1.0 MHz
8.0 kHz
V REF
CS
Figure 1. AD28MSP02 Block Diagram
The IIR low-pass filter is a 10th-order elliptic filter with a passband edge at 3.7 kHz and a stopband attenuation of 65 dB at 4 kHz. This filter has the following specifications: Filter type: Sample frequency: Passband cutoff:* Passband ripple: Stopband cutoff: Stopband ripple: 10th-order low-pass elliptic IIR 40.0 kHz 3.70 kHz 0.2 dB 4.0 kHz -65.00 dB
The high-pass filter is a 4th-order elliptic filter with a passband cutoff at 150 Hz. Stopband attenuation is 25 dB. This filter has the following specifications: Filter type: Sample frequency: Passband cutoff: Passband ripple: Stopband cutoff: Stopband ripple: 4th-order high-pass elliptic IIR 8.0 kHz 150.0 Hz 0.2 dB 100.0 Hz -25.00 dB
*The passband cutoff frequency is defined to be the last point in the passband that meets the passband ripple specification. (Note that these specifications apply only to this filter, and not to the entire ADC. The specifications can be used to perform further analysis of the exact characteristics of the filter, for example using a digital filter design software package.)
(Note that these specifications apply only to this filter, and not to the entire ADC. The specifications can be used to perform further analysis of the exact characteristics of the filter, for example using a digital filter design software package.)
Figure 3 shows the frequency response of the high-pass filter.
0
Figure 2 shows the frequency response of the IIR low-pass filter.
0
-20
LOG MAGNITUDE - dB
-20
LOG MAGNITUDE - dB
-40
-40
-60
-60
-80
-80
-100 0 60 120 180 FREQUENCY - Hz 240 300
-100 2000
2600
3200
3800
4400
5000
FREQUENCY - Hz
Figure 3. High-Pass Filter Frequency Response
Figure 2. IIR Low-Pass Filter Frequency Response
High-Pass Filter
Passband ripple is 0.2 dB for the combined effects of the ADC's digital filters (i.e., high-pass filter and IIR low-pass of the decimation filter) in the 300 Hz-3400 Hz passband. The output of the ADC is transferred to the AD28MSP02's serial port (SPORT) at an 8 kHz rate, for transmission to the host DSP processor. Maximum group delay in the ADC will not exceed 1 ms in the region from 300 Hz to 3 kHz.
The digital high-pass filter removes frequency components at the low end of the spectrum; it attenuates signal energy below the passband of the converter. The high-pass filter can be bypassed by setting the ADBY bit (Bit 3) of the AD28MSP02's control register.
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PIN DESCRIPTIONS D/A CONVERSION
Pin Name VINNORM VFBNORM VINAUX VFBAUX VOUTP VOUTN VREF MCLK
I/O/Z Function I O I O O O O I Analog input to inverting terminal of NORM input amplifier. Output terminal of NORM amplifier. Analog input to inverting terminal of AUX input amplifier. Output terminal of AUX amplifier. Analog output from noninverting terminal of differential output amplifier. Analog output from inverting terminal of differential output amplifier. On-chip bandgap voltage reference (2.5 V 10%). Master clock input; frequency must equal 13.0 MHz to guarantee listed specifications. Serial clock used to clock data or control bits to and from the serial port (SPORT). The frequency of SCLK is equal to the frequency of the master clock (MCLK) divided by 5. SCLK is 3-stated when CS is low. Serial data input of SPORT. Both data and control information are input on this pin. Input at SDI is ignored when CS is low. Serial data output of SPORT. Both data and control information are output on this pin. SDO is 3-stated when CS is low. Framing signal for SDI serial transfers. Input at SDIFS is ignored when CS is low. Framing signal for SDO serial transfers. SDOFS is 3-stated when CS is low. Configures AD28MSP02 for either data or control information transfers (via SPORT). Active-high chip select. Can be used to 3-state the SPORT interface; when CS is low, the SCLK, SDO, and SDOFS outputs are 3-stated and the SDI and SDIFS inputs are ignored. If CS is deasserted during a serial data transfer, the 16-bit word being transmitted is lost. Active low reset signal; resets Control Register and clears digital filters. RESET does not 3-state the SPORT outputs (SCLK, SDO, SDOFS). Analog supply voltage; nominal +5 V. Analog ground. Digital supply voltage; nominal +5 V. Digital ground.
The D/A conversion circuitry of the AD28MSP02 consists of a sigma-delta digital-to-analog converter (DAC), an analog smoothing filter, a programmable gain amplifier, and a differential output amplifier.
DAC
The AD28MSP02's sigma-delta DAC implements digital filters and a sigma-delta modulator with the same characteristics as the filters and modulator of the ADC. The DAC consists of a digital high-pass filter, an anti-imaging interpolation filter, and a digital sigma-delta modulator. The DAC receives 16-bit samples from the host DSP processor via AD28MSP02's serial port at an 8 kHz rate. If the host processor fails to write a new value to the serial port, the existing (previous) data is read again. The data stream is filtered first by the DAC's high-pass filter and then by the anti-imaging interpolation filter. These filters have the same characteristics as the ADC's anti-aliasing decimation filter and digital high-pass filter. The output of the interpolation filter is fed to the DAC's digital sigma-delta modulator, which converts the 16-bit data to 1-bit samples at a 1.0 MHz rate. The modulator noise-shapes the signal such that errors inherent to the process are minimized in the passband of the converter. The bit stream output of the sigmadelta modulator is fed to the AD28MSP02's analog smoothing filter where it is converted to an analog voltage.
High-Pass Filter
SCLK
O/Z
SDI
I
SDO
O/Z
SDIFS
I
The digital high-pass filter of the AD28MSP02's DAC has the same characteristics as the high-pass filter of the ADC. The high-pass filter removes frequency components at the low end of the spectrum; it attenuates signal energy below the passband of the converter. The DAC's high-pass filter can be bypassed by setting the DABY bit (Bit 2) of the AD28MSP02's control register. The high-pass filter is a 4th-order elliptic filter with a passband cutoff at 150 Hz. Stopband attenuation is 25 dB. This filter has the following specifications: Filter type: Sample frequency: Passband cutoff: Passband ripple: Stopband cutoff: Stopband ripple: 4th-order high-pass elliptic IIR 8.0 kHz 150.0 Hz 0.2 dB 100.0 Hz -25.00 dB
SDOFS
O/Z
DATA/CNTRL I
CS
I
(Note that these specifications apply only to this filter, and not to the entire DAC. The specifications can be used to perform further analysis of the exact characteristics of the filter, for example using a digital filter design software package.)
Figure 3 shows the frequency response of the high-pass filter.
Interpolation Filter
RESET
I
VCC GNDA VDD GNDD
The anti-imaging interpolation filter contains two stages. The first stage is an IIR low-pass filter that interpolates the data rate from 8 kHz to 40 kHz and removes images produced by the interpolation process. The output of this stage is then interpolated to 1.0 MHz and fed to the second stage, a sinc4 digital filter that attenuates images produced by the 40 kHz to 1.0 MHz interpolation process.
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The IIR low-pass filter is a 10th-order elliptic filter with a passband edge at 3.70 kHz and a stopband attenuation of 65 dB at 4 kHz. This filter has the following specifications: Filter type: Sample frequency: Passband cutoff:* Passband ripple: Stopband cutoff: Stopband ripple: l0th-order low-pass elliptic IIR 40.0 kHz 3.70 kHz 0.2 dB 4.0 kHz -65.00 dB
SERIAL PORT
The AD28MSP02 communicates with a host processor via the bidirectional synchronous serial port (SPORT). The SPORT is used to transmit and receive digital data and control information. All serial transfers are 16 bits long, MSB first. Data bits are transferred at the serial clock rate (SCLK). SCLK equals the master clock frequency divided by 5. SCLK = 2.6 MHz for the master clock frequency MCLK = 13.0 MHz.
Host Processor Interface
*The passband cutoff frequency is defined to be the last point in the passband that meets the passband ripple specification. (Note that these specifications apply only to this filter, and not to the entire DAC. The specifications can be used to perform further analysis of the exact characteristics of the filter, for example using a digital filter design software package.)
The AD28MSP02-to-host processor interface is shown in Figure 4.
AD28MSP02
SDO SDOFS SCLK DATA/CNTRL SDI SDIFS
Host Processor
SERIAL DATA RECEIVE RECEIVE FRAME SYNC SERIAL CLOCK FLAG SERIAL DATA TRANSMIT TRANSMIT FRAME SYNC
Figure 2 shows the frequency response of the IIR low-pass filter. Passband ripple is 0.2 dB for the combined effects of the DAC's digital filters (i.e., high-pass filter and IIR low pass of the interpolation filter) in the 300 Hz-3400 Hz passband.
Analog Smoothing Filter and Programmable Gain Amplifier
The programmable gain amplifier (PGA) can be used to adjust the output signal level by -15 dB to +6 dB. This gain is selected by bits 7-9 (OG0, OG1, OG2) of the AD28MSP02's control register. The AD28MSP02's analog smoothing filter consists of a 2ndorder Sallen-Key continuous-time filter and a 3rd-order switched capacitor filter. The Sallen-Key filter has a 3 dB point at approximately 80 kHz.
Differential Output Amplifier
Figure 4. AD28MSP02-to-Host Processor Interface
Table I describes the SPORT signals and how they are used to communicate with the host processor. The AD28MSP02's chip select (CS) must be held high to enable SPORT operation. CS can be used to 3-state the SPORT pins and disable communication with the host processor. To use the ADSP-2101 or ADSP-2111 as host DSP processor for the AD28MSP02, the following connections can be used (as shown in Figure 5): AD28MSP02 Pin SCLK SDO SDOFS SDI SDIFS DATA/CNTRL - - - - - - ADSP-2101/2111 Pin SCLK0 DR0 RFS0 DT0 TFS0 FO (Flag Output)
The AD28MSP02's analog output (VOUTP, VOUTN) is produced by a differential output amplifier. The differential amplifier can drive loads of 2 k or greater and has a maximum differential output voltage swing of 3.156 V peak-to-peak (3.17 dBm0). The output signal is dc-biased to the AD28MSP02's on-chip voltage reference (VREF) and can be ac-coupled directly to a load or dc-coupled to an external amplifier. Refer to "Analog Output" in the "Design Considerations" section of this data sheet for more information. The VOUTP-VOUTN outputs must be used as differential outputs; do not use either as a single-ended output.
Table I. SPORT Signals
Signal Name SCLK SDO SDOFS SDI SDIFS
Description Serial clock Serial data output Serial data output frame sync Serial data input Serial data input frame sync
Generated By AD28MSP02 AD28MSP02 AD28MSP02 Host Processor Host Processor
Signal State When RESET Low (CS High) Low Low Low -- --
Signal State During Powerdown (CS High) Active Active* Low -- --
(CS must be held high to enable SPORT operation.)
*Outputs last data value that was valid prior to entering powerdown.
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Note that the ADSP-2101's SPORT0 communicates with the AD28MSP02's SPORT while the ADSP-2101's Flag Output (FO) is used to signal the AD28MSP02's DATA/CNTRL input. SPORT1 on the ADSP-2101 must be configured for flags and interrupts in this system. Figure 6 shows an ADSP-2101 assembly language program that initializes the AD28MSP02 and implements digital loopback through the DSP processor.
AD28MSP02
SDO SDOFS DR0 RFS0 SCLK0 FO DT0 TFS0
ADSP-2101
SCLK DATA/CNTRL SDI SDIFS
Figure 5. AD28MSP02-to-ADSP-2101 Interface
{ This ADSP-2101 program initializes the AD28MSP02 } { and executes a loopback, or talk-through, routine. } .MODULE/ABS = 0/BOOT = 0 test1; resetv: irq2v: st0x: sr0x: JUMP begin; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; ax0 = rx0; tx0 = ax0; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RESET FLAG OUT; AX0 = 0x2A0F; DM (0x3FF6) = AX0; AX0 = 0x101F; DM (0x3FFF) = AX0; IMASK= 0x10; AX0 = 0x30; TX0 = AX0; IDLE; NOP; IMASK= 0x08; SET FLAG OUT; wait: JUMP wait; NOP; { Wait for receive interrupt } {restart} {IRQ2} {SPORT0 Tx} {SPORT0 Rx}
irq1v: irq0v: timerv: begin:
{irq1} {irq0}
{Configure ADSP-2101 SPORT0 for } { ext. SCLK, ext. RFS, int. TFS } { Enable ADSP-2101 SPORT0, } { configure SPORT1 for Flag Out } { Write control word to take} { AD28MSP02 out of powerdown }
.ENDMOD;
Figure 6. ADSP-2101 Digital Loopback Routine
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Serial Data Output
The AD28MSP02's SPORT will begin transmitting data to the host processor at an 8 kHz rate when the PWDD and PWDA bits (Bits 4, 5) of the control register are set to 1. In the program shown in Figure 6, the instructions AX0 = 0x30; { Write control word to take } TX0 = AX0; { AD28MSP02 out of powerdown } accomplish this by writing 0x30 to the AD28MSP02's control register. There is a short start-up time (after the end of this control register write) before the AD28MSP02 raises SDOFS and begins transmitting data; see Figure 11. At the 13 MHz MCLK frequency, data is transmitted at an 8 kHz rate with a single 16-bit word transmitted every 125 s. While data is being output, the AD28MSP02 asserts SDOFS at an 8 kHz rate. Each 16-bit word transfer begins one serial clock cycle after SDOFS is asserted.
Serial Data Input
Each bit of a 16-bit data word is thus clocked into the AD28MSP02 on the falling edge of SCLK (MSB first). If SDIFS is asserted high again before the end of the present data word transfer, it is not recognized until the falling edge of SCLK in the last (LSB) cycle. (Note: Exact SPORT timing requirements are defined in the "Specifications" section of this data sheet.)
CONTROL REGISTER
The AD28MSP02's control register configures the device for various modes of operation including ADC and DAC gain settings, ADC input mux selection, filter bypass, and powerdown. The AD28MSP02's host processor can read and write to the control register through the AD28MSP02's serial port (SPORT) by driving the DATA/CNTRL pin low. The control register is cleared (set to 0x0000) when the AD28MSP02 is reset.
Control Register Writes
The host processor must initiate data transfers to the AD28MSP02 by asserting the serial data input frame sync (SDIFS) high. The 16-bit word transfer begins one serial clock cycle after SDIFS is asserted. The DATA/CNTRL line must be driven high when SDIFS is driven high. The host processor must assert SDIFS shortly after the rising edge of SCLK and must maintain SDIFS high for one cycle. Data is then driven from the host processor (to the SDI input) shortly after the rising edge of the next SCLK and is clocked into the AD28MSP02 on the falling edge of SCLK in that cycle.
To write the control register, the host processor must assert DATA/CNTRL low when it asserts SDIFS. If the MSB of the bit stream is also low, the SPORT recognizes the incoming serial data as a new control word and copies it to the AD28MSP02's control register. The format for the control word write is shown in Table II; reserved Bits 10-15 must be set to zero.
Table II. Control Word Write Format
15 0 0 1 2 3 4 5 7-9 10-15 Gain
14 0
13 0 IPS IMS DABY ADBY PWDA PWDD OG2-OG0
12 0
11 0
10 0
9 OG2
8 OG1
7 OG0
6 0
5 PWDD
4
3
2
1
0 IPS
PWDA ADBY
DABY IMS
Analog input preamplifier select: 1 = insert (+20 dB), 0 = bypass (0 dB) Analog input multiplexer select: 1 = AUX input, 0 = NORM input DAC high-pass filter bypass select: 0 = insert, 1 = bypass ADC high-pass filter bypass select: 0 = insert, 1 = bypass Powerdown analog: 0 = powerdown, 1 = operating Powerdown digital: 0 = powerdown, 1 = operating Analog output gain setting (for D/A output PGA) Reserved OG2 0 0 0 0 1 1 1 1 OG1 0 0 1 1 0 0 1 1 OG0 0 1 0 1 0 1 0 1
+6 dB +3 dB 0 dB -3 dB -6 dB -9 dB -12 dB -15 dB
Gain settings are accurate within 0.6 dB. (Control Register is set to 0x0000 at RESET. Reserved Bits 10-15 must be set to 0 for all Control Register writes.)
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Table III. Control Word Read Format Read Request
15 1
14 0
13 0
12 0
11 0
10 0
9 0
8 0
7 0
6 0
5 0
4 0
3 0
2 0
1 0
0 0
Read Ready
15 1
14 1
13 0
12 0
11 0
10 0
9 0
8 0
7 0
6 0
5 0
4 0
3 0
2 0
1 0
0 0
Control Register Reads
To read the control register, the host processor must transfer two control words. For each transfer, the DATA/CNTRL pin must be low when SDIFS is asserted. If the MSB of the bit stream is high, the SPORT recognizes the incoming serial data as a request for control information. The protocol for reading the control register is as follows: 1. The host processor sends a "Read Request" control word to the AD28MSP02. Since the MSB of this control word is high, the SPORT recognized the incoming serial data as a read request and does not overwrite the control register. 2. When the AD28MSP02 receives the read request, it finishes any data transfers in progress and waits for a "Read Ready" control word. 3. The host processor then transfers a "Read Ready" control word to the AD28MSP02. Upon receiving this control word, the AD28MSP02 transfers the control register contents to the host processor via the SPORT. 4. When the SPORT completes the control register transfer, it immediately resumes transmitting data at an 8 kHz rate. This scheme allows any data transfers in progress to be completed and resolves any ambiguities between data and control words. The format for the read control words is shown in Table III.
DESIGN CONSIDERATIONS Analog Input
In the circuit shown in Figure 7, scaling of the analog input is achieved by the resistors RIN and RFB. The input signal gain, -RFB/RIN, can be adjusted from -12 dB to +26 dB by varying the values of these resistors. The AD28MSP02's on-chip 20 dB preamplifier can be enabled when there is not enough gain in the input circuit; the preamplifier is configured by Bit 0 (IPS) of the control register. Total gain must be configured to ensure that a full-scale input signal (at CIN in Figure 7) produces a signal level at the input to the sigma-delta modulator of the ADC that does not exceed VINMAX, which is specified under "Analog Interface Electrical Characteristics." If the total gain is increased above unity, signal-to-noise (SNR + THD) performance will not meet the listed specifications.
C FB VFB NORM C IN INPUT SIGNAL R IN R FB VIN NORM
VFB AUX VIN AUX
MUX
VOLTAGE REFERENCE
The analog input signal to the AD28MSP02 must be ac-coupled. Figure 7 shows the recommended input circuit for the AD28MSP02's analog input pin (either VINNORM or VINAUX). The circuit of Figure 7 implements a first-order low-pass filter with a 3 dB point at 20 kHz; this is the only filter that must be implemented external to the AD28MSP02 to prevent aliasing of the sampled signal. Since the AD28MSP02's ADC uses a highly oversampled approach that transfers the bulk of the anti-aliasing filtering into the digital domain, the off-chip anti-aliasing filter need only be of low order.
AD28MSP02
Figure 7. Recommended Analog Input Circuit
The dc biasing of the analog input signal is accomplished with an on-chip voltage reference which nominally equals 2.5 V. The input signal must be ac-coupled with an external coupling capacitor (CIN). CIN and RIN should be chosen to ensure a coupling corner frequency of 30 Hz. CIN should be 0.1 F or larger.
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To select values for the components shown in Figure 7, use the following equations: Gain = RFB RIN Figure 9 shows a simple circuit providing a differential output with ac coupling. The capacitor of this circuit (COUT) is optional; if used, its value can be chosen as follows: COUT = 1 (60 ) RL
CIN =
1 60 RIN
AD28MSP02
CFB =
1 3 (2 )(20 x 10 ) RFB
10 k RFB, RIN 50 k 150 pF CFB 600 pF Figure 8 shows an example of a typical input circuit configured for 0 dB gain. The circuit's diodes are used to prevent the input signal from exceeding maximum limits.
VCC 330pF VFBNORM 10k 1.0F 10k 20k VINNORM
C OUT VOUTP RL
VOUT N C OUT
Figure 9. Example Circuit for Differential Output
INPUT SIGNAL
GNDA
VFBAUX VINAUX
MUX
The VOUTP-VOUTN outputs must be used as differential outputs; do not use either as a single-ended output. Figure 10 shows an example circuit which can be used to convert the differential output to a single-ended output. The circuit uses a differential-to-single-ended amplifier, the Analog Devices SSM2141.
AD28MSP02
+12 V
VOLTAGE REFERENCE
0.1 F GND A
AD28MSP02
Figure 8. Example Analog Input Circuit for 0 dB Gain
Analog Output
5 VOUT
7 VOUT P SSM2141 1 4 VOUT N
The AD28MSP02's differential analog output (VOUTP, VOUTN) is produced by an on-chip differential amplifier. The differential amplifier can drive a minimum load of 2 k (RL 2 k) and has a maximum differential output voltage swing of 3.156 V peak-to-peak (3.17 dBm0). The differential output can be ac-coupled directly to a load or dc-coupled to an external amplifier.
GND A 0.1 F GNDA -12 V
Figure 10. Example Circuit for Single-Ended Output
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Serial Output Startup Time
The AD28MSP02 begins transmitting data to the host processor after it is taken out of powerdown. To take the AD28MSP02 out of powerdown, the host processor writes a control word to the AD28MSP02. The start-up time (from the start of this control word write) before the AD28MSP02 begins transmitting data is shown in Figure 11.
PC Board Layout Considerations
traces (such as digital clocks and analog signals) are as short as possible. Each +5 V digital supply pin, VDD, of the AD28MSP02 (SOIC Pins 20, 21) should be bypassed to ground with a 0.1 F capacitor. These capacitors should be low inductance, monolithic, ceramic, and surface-mount. The capacitor leads and PC board traces should be as short as possible to minimize inductive effects. In addition, a 10 F capacitor should be connected between VDD and ground, near the PC board power connection.
MCLK Frequency
Separate analog and digital ground planes should be provided for the AD28MSP02 in order to ensure the characteristics of the device's ADC and DAC. The two ground planes should be connected at a single point--this is often referred to as a "Star" or "Mecca" grounding configuration. The point of connection may be at the system power supply, at the PC board power connection, or at any other appropriate location. Because ground loops increase susceptibility to EMF, multiple connections between the analog and digital ground planes should be avoided. The ground planes should be designed such that all noisesensitive areas are isolated from one another and critical signal
The sigma-delta converters and digital filters of the AD28MSP02 are specifically designed to operate at a master clock (MCLK) frequency of 13.0 MHz. MCLK must equal 13.0 MHz to guarantee the filter characteristics and sample rate of the ADC and DAC. The AD28MSP02 is not tested or characterized at any other clock frequency. A low cost crystal with a different frequency, for example 12.288 MHz, can be used for the master clock input; in this case, however, the AD28MSP02 is not guaranteed to meet the specifications listed in this data sheet.
SCLK
DATA/ CNTRL SDIFS
SDI
MSB
2nd MSB
SDOFS
POWERUP CONTROL WORD WRITTEN TO AD28MSP02
SDO 410 SCLK CYCLES (2050 MCLK CYCLES)
MSB
2nd MSB
FIRST DATA WORD TRANSMITTED FROM AD28MSP02
Figure 11. Serial Output Startup Time
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DEFINITION OF SPECIFICATIONS Absolute Gain Idle Channel Noise
Absolute gain is a measure of converter gain for a known signal. Absolute gain is measured with a 1.0 kHz sine wave at 0 dBm0. The absolute gain specification is used as a reference for gain tracking error specification.
Gain Tracking Error
Idle channel noise is defined as the total signal energy measured at the output of the device when the input is grounded (measured in the frequency range 300 Hz-3400 Hz). Crosstalk Crosstalk is defined as the ratio of the amplitude of a full-scale signal appearing on one channel to the amplitude of the same signal which couples onto the adjacent channel. Crosstalk is expressed in dB.
Power Supply Rejection
Gain tracking error measures changes in converter output for different signal levels relative to an absolute signal level. The absolute signal level is 1 kHz at 0 dBm0 (equal to absolute gain). Gain tracking error at 0 dBm0 is 0 dB by definition.
SNR + THD
Signal-to-noise ratio plus total harmonic distortion is defined to be the ratio of the rms value of the measured input signal to the rms sum of all other spectral components in the frequency range 300 Hz-3400 Hz, including harmonics but excluding dc.
Intermodulation Distortion
Power supply rejection measures the susceptibility of a device to noise on the power supply. Power supply rejection is measured by modulating the power supply with a sine wave and measuring the noise at the output (relative to 0 dB).
Group Delay
With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which neither m or n are equal to zero. For final testing, the second order terms include (fa + fb) and (fa - fb), while the third order terms include (2fa + fb), (2fa - fb), (fa + 2fb), and (fa - 2fb).
Group delay is defined as the derivative of radian phase with respect to radian frequency, ()/. Group delay is a measure of average delay of a system as a function of frequency. A linear system with a constant group delay has a linear phase response. The deviation of group delay away from a constant indicates the degree of nonlinear phase response of the system.
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AD28MSP02
SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
K Grade Parameter VDD, VCC TAMB Supply Voltage Ambient Operating Temperature Min 4.50 0 Max 5.50 +70 Min 4.50 -40
B Grade Max 5.50 +85 Unit V C
Refer to Environmental Conditions for information on case temperature and thermal specifications.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V Input Voltage . . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V Output Voltage Swing . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V Operating Temperature Range (Ambient) . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . . -55C to +150C Lead Temperature (5 sec) SOIC . . . . . . . . . . . . . . . . . +280C
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD SENSITIVITY
The AD28MSP02 features proprietary input protection circuitry to dissipate high-energy discharges (Human Body Model). Per method 3015 of MIL-STD-883C, the AD28MSP02 has been classified as a Class 1 device. Proper ESD precautions are strongly recommended to avoid functional damage or performance degradation. Charges readily accumulate on the human body and test equipment and discharge without detection. Unused devices must be stored in conductive foam or shunts, and the foam should be discharged to the destination socket before devices are removed.
WARNING!
ESD SENSITIVE DEVICE
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AD28MSP02
DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS
Symbol VIH VIL VOH VOL IIH IIL IOZL IOZH CI
Parameter Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage High Level Input Current Low Level Input Current Low Level Output 3-State Leakage Current High Level Output 3-State Leakage Current Digital Input Capacitance
Min 2.4
Typ
Max 0.8
Unit V V V V A A A A pF
Test Condition VDD = max VDD = min VDD = min, IOH = -0.5 mA VDD = min, IOL = 2 mA VDD = max, VIN = max VDD = max, VIN = 0 V VDD = max, VIN = max VDD = max, VIN = 0 V
2.4 0.4 10 10 10 10 10
ANALOG INTERFACE ELECTRICAL CHARACTERISTICS
Symbol ADC: IL RI CIL VINMAX DAC: RO VOOFF COL VVREF VO RL
Parameter
Min
Typ
Max
Unit
Input Leakage Current at VINNORM, VINAUX Input Resistance1 at VINNORM, VINAUX Input Load Capacitance1 at VINNORM, VINAUX Maximum Input Range2 Output Resistance1, 3 Output DC Offset4 Output Load Capacitance3 Voltage Reference (VREF) Maximum Voltage Output Swing (p-p) Across RL Single-Ended Differential Load Resistance3
10 100 10 3.156 1 400 100 2.75 3.156 6.312 2
nA M pF V p-p mV pF V V V k
2.25
Test Conditions for all analog interface tests: Unity input gain, A/D 20 dB preamplifier bypassed, D/A PGA set for 0 dB gain, no load on analog output (VOUTP-VOUTN). 1 Guaranteed but not tested. 2 At input to sigma-delta modulator of ADC. 3 At VOUTP-VOUT N. 4 Between VOUTP and VOUTN.
POWER DISSIPATION
Symbol VCC VDD IDD P1 IDD P0
Parameter Analog Operating Voltage Digital Operating Voltage Operating Current Active1 Power Dissipation Active1 Operating Current Inactive2 Power Dissipation Inactive2
Min 4.5 4.5
Max 5.5 5.5 40 200 0.5 2.5
Unit V V mA mW mA mW
Test conditions: V DD = VCC = 5.0 V, MCLK frequency 13.0 MHz, no load on digital pins, analog inputs ac-coupled to ground, no load on analog output (VOUTP-VOUTN) I Active: AD28MSP02 operational (PWDD and PWDA set to 1 in control register). 2 Inactive: AD28MSP02 in powerdown state (PWDD and PWDA set to 0 in control register) and MCLK tied to VDD.
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AD28MSP02
TIMING PARAMETERS Clock Signals
Parameter Timing Requirement: tMCK tMKL tMKH Switching Characteristic: tSCK tSKL tSKH MCLK Period MCLK Width Low MCLK Width High SCLK Period SCLK Width Low SCLK Width High
Min 76.9 0.5tMCK - 10 0.5tMCK - 10 5tMCK 3tMCK - 10 2tMCK - 10
t MCK
MCLK
Max 76.9 0.5tMCK + 10 0.5tMCK + 10 3tMCK + 10 2tMCK + 10
Unit ns ns ns ns ns ns
t MKL
t MKH
tSCK
SCLK
tSKL
t SKH
Figure 12. Clock Signals
Serial Port 3-State
Parameter Switching Characteristic: tSPD tSPE tSPV CS Low to SDO, SDOFS, SCLK Disable CS High to SDO, SDOFS, SCLK Enable CS High to SDO, SDOFS, SCLK Valid
Min
Max 25
Unit ns ns ns
0 10
tSPV
t SPD
CS
tSPE
SDO SDOFS SCLK
Figure 13. Serial Port 3-State
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AD28MSP02
Serial Ports
Parameter Timing Requirements: tSCS tSCH tDCS tDCH Switching Characteristic: tRD tRH tSCDH tSCDD SDI/SDIFS Setup before SCLK Low SDI/SDIFS Hold after SCLK Low DATA/CNTRL Setup before SCLK Low DATA/CNTRL Hold after SCLK Low SDOFS Delay from SCLK High SDOFS Hold after SCLK High SDO Hold after SCLK High SDO Delay from SCLK High
t SCK
SCLK
Min 10 10 10 10
Max
Unit ns ns ns ns
15 0 0 30
ns ns ns ns
tSCS
SDIFS
t SCH
DATA/CNTRL
t DCS t DCH
SDI MSB
t SCH
2ND MSB 3RD MSB
t SCS t RD
SDOFS
t RH t SCDD
SDO
t SCDH
Figure 14. Serial Ports
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AD28MSP02
DIGITAL TEST CONDITIONS
3.0V 1.5V 0.0V
I
OL
DIGITAL INPUT
DIGITAL OUTPUT
2.0V 1.5V 0.8V
TO DIGITAL OUTPUT PIN 50pF
+1.5V
Figure 15. Voltage Reference Levels for AC Measurements
I
OH
Figure 16. Equivalent Device Loading for AC Measurements (Includes All Fixtures)
GAIN
Parameter ADC Absolute Gain ADC Gain Tracking Error DAC Absolute Gain DAC Gain Tracking Error
Min -0.2 -0.1 -0.2 -0.1
Typ 0 0 0 0
Max 0.2 0.1 0.2 0.1
Unit dBm0 dBm0 dBm0 dBm0
Test Conditions 1.0 kHz, 0 dBm0 1.0 kHz, +3 to -50 dBm0 1.0 kHz, 0 dBm0 1.0 kHz, +3 to -50 dBm0
FREQUENCY RESPONSE
Input Freq (Hz) 0 100 150 200 300 1000 2000 3000 3400 3700 4000 >4000
Min Output (dB) - - -0.3 -0.3 -0.2 -0.2 -0.2 -0.2 -0.2 -0.3 - -
Max Output (dB) -25 -25 +0.3 +0.3 +0.2 +0.2 +0.2 +0.2 +0.2 +0.3 -60 -60
Frequency responses of ADC and DAC measured with input at audio reference level (the input level that produces an output level of -10 dBm0), with 20 dB preamplifier bypassed and input gain of 0 dB. The in-band ripple shall not exceed 0.2 dB.
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AD28MSP02
NOISE AND DISTORTION
Parameter ADC Intermodulation Distortion DAC Intermodulation Distortion ADC Idle Channel Noise DAC Idle Channel Noise ADC Crosstalk DAC Crosstalk ADC Power Supply Rejection DAC Power Supply Rejection ADC Group Delay1 DAC Group Delay1
1
Min
Max -70 -70 72 72 -65 -65 -55 55 1 1
Unit dB dB dBm0 dBm0 dB dB dB dB ms ms
Test Conditions
ADC input signal level: 1.0 kHz, 0 dBm0 DAC input at idle ADC input signal level: analog ground DAC output signal level: 1.0 kHz, 0 dBm0 Input signal level at VCC and VDD pins: 1.0 kHz, 100 mV p-p sine wave Input signal level at VCC and VDD pins: 1.0 kHz, 100 mV p-p sine wave 300-3000 Hz 300-3000 Hz
Guaranteed but not tested.
70 60 50
SNR+THD - dB
40 30 20 10 0
-10 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 VIN - dBm0
0 3.17
Figure 17. SNR + THD vs. VIN
ORDERING GUIDE
Part Number AD28MSP02KN AD28MSP02KR AD28MSP02BN AD28MSP02BR
Temperature Range 0C to +70C 0C to +70C -40C to +85C -40C to +85C
Package 24-Pin Plastic DIP 28-Lead SOIC 24-Pin Plastic DIP 28-Lead SOIC
Package Option* N-24 R-28 N-24 R-28
*N = Plastic DIP, R = Small Outline (SOIC).
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AD28MSP02
PIN CONFIGURATIONS 24-Pin Plastic DIP
VCC V
REF P
1 2 3 4 5 6 7 8 9 10 11 12 TOP VIEW (Not to Scale)
24 23 22 21 20
VINNORM VFB
NORM
VOUT VOUT
VINAUX VFB
AUX
N A
GND GND
GNDA GNDD
D
AD28MSP02
19
DATA/CNTRL SDO SDOFS SDI SDIFS SCLK
18 VDD 17 16 15 14 13 NC NC RESET CS MCLK
NC = NO CONNECTION
28-Lead SOIC
VCC VREF VOUTP VOUTN GND
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 TOP VIEW (Not to Scale)
28
VIN
NORM
27 VFB NORM 26 VIN AUX 25 VFBAUX 24 GND
A
GNDA GND GND
D D
AD28MSP02
23 22 21 20 19 18 17 16
GNDD GND VDD V
DD D
DATA/CNTRL SDO SDOFS SDI SDIFS SCLK
NC NC RESET CS
15 MCLK
NC = NO CONNECTION
REV. 0
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AD28MSP02
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Pin Plastic DIP (N-24)
24 PIN 1 1 1.275 (32.30) 1.125 (28.60) 0.210 (5.33) MAX 0.200 (5.05) 0.125 (3.18) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.070 (1.77) 0.045 (1.15) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN SEATING PLANE 0.015 (0.381) 0.008 (0.204) 12 13 0.280 (7.11) 0.240 (6.10)
0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93)
28-Lead Wide-Body SOIC (R-28)
28
15 0.2992 (7.60) 0.2914 (7.40)
PIN 1 1 14
0.4193 (10.65) 0.3937 (10.00)
0.7125 (18.10) 0.6969 (17.70)
0.1043 (2.65) 0.0926 (2.35)
0.0291 (0.74) x 45 0.0098 (0.25)
0.0118 (0.30) 0.0040 (0.10)
0.0500 (1.27) BSC
0.0192 (0.49) 0.0138 (0.35)
0.0125 (0.32) 0.0091 (0.23)
8 0
0.0500 (1.27) 0.0157 (0.40)
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C1672-8-6/92
PRINTED IN U.S.A.

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